1. Field of the Invention
The present invention relates to a memory device having a pipe counter. In particular, the present invention relates to a memory device having a pipe counter which can perform the same functions as a conventional pipe counter while reducing the circuit area and decreasing the driving current of the counter, by applying the concept of a ring counter to a pipe counter used in a data output terminal of DRAM.
2. Description of the Prior Art
Typically, counters used in the data output terminals of DRAM employ pipe counters.
A schematic diagram of a conventional pipe counter circuit is shown in FIG. 1. As shown in FIG. 1, a conventional pipe counter includes a NOR-gate NOR1 for NORing a column latency CL signal and a power signal passed through an inverter INV1 so as to output the resulting signals to pipe counter input terminals 1, 2 and 3, respectively; pipe counter input terminals 1, 2 and 3 having NAND-gates 11, 21 and 31 for NANDing the signals output from the NOR-gate NOR1, and for outputting the resulting signals through respective delay sections 12, 22 and 32 to pipe counter output sections 4, 5 and 6, respectively; and pipe counter outputs sections 4, 5 and 6 driven in response to the signals input from the respective pipe counter input terminals 1, 2 and 3, for outputting respective pipe counter signals pipe counter 0, pipe counter 1, and pipe counter 2.
In operation, a level row address signal LRAS representing a read mode and a clock are input to drive the circuit.
The pipe counter output section 4 is driven by means of a N-MOS transistor N41 which is driven in response to the signal outputted from the input terminal 1, and the respective pipe counter input terminals 1, 2 and 3 and the respective pipe counter output sections 4, 5 and 6 have the same structure.
The operation of a conventional pipe counter constructed as above will be explained below by reference to the timing diagram of FIG. 2.
When the power signal (FIG. 2A) reaches a high level and the LRAS signal (FIG. 2B) reaches a high level, both a low level (FIG. 2C) input through the CL signal terminal and a low level of the power signal passed through the inverter INV1 are inputted into the NOR-gate NOR1.
Therefore, the NOR-gate NOR1 outputs a high level, and the NAND-gate NAND11, one end of which receives the output signal from the NOR1, outputs a high level (from node 1), thereby turning on the N-MOS transistor N41 within the pipe counter output terminal 4.
Next, the node (node 2) connected to the drain terminal of the N-MOS transistor N41 reaches a low level, and the P-MOS transistor P41 connected to it is turned on. Accordingly, the level of the pipe counter 0 node (node 3) becomes a high level, thereby outputting a signal to the pipe counter output terminal in response to the clocks (FIG. 2D).
With signals other than those (for example, Cl signal : H, power signal :L), the pipe counter circuit does not work.
However, the pipe counter operating as above involves some problems in constructing the circuit so as to operate only in read mode.
In other words, the problem is that the circuit as constructed is automatically operated when the power is turned on and the LRAS signal is at a high level.
Also, as explained above, since the pipe counter is constructed using transistor delays, a plurality of transistors having a large size is required.
Also, additional control transistors for controlling the delay transistors are required.
Therefore, there is the problem that the driving current of the transistors is increased and a large layout is necessary for the large transistors.